aboutsummaryrefslogtreecommitdiff
path: root/src/main.cpp
diff options
context:
space:
mode:
authorgingerBill <gingerBill@users.noreply.github.com>2024-09-02 00:20:04 +0100
committerGitHub <noreply@github.com>2024-09-02 00:20:04 +0100
commit16c5c69a4079652e930d897823446b7e7a65bd2f (patch)
tree2543c3c65ca653bcc0ed13da59775d4b314d57e7 /src/main.cpp
parent39b49cb6fbf5f717bb0b01c6449d37f99ffd9b48 (diff)
parent28c643d23f989937c8d530b49a2369e8cd9d39e2 (diff)
Merge pull request #4175 from laytan/riscv-compilerdev-2024-09
Support RISC-V for the compiler itself
Diffstat (limited to 'src/main.cpp')
-rw-r--r--src/main.cpp6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/main.cpp b/src/main.cpp
index 5131bdc21..34f3c832d 100644
--- a/src/main.cpp
+++ b/src/main.cpp
@@ -3252,6 +3252,12 @@ int main(int arg_count, char const **arg_ptr) {
gb_printf_err("missing required target feature: \"%.*s\", enable it by setting a different -microarch or explicitly adding it through -target-features\n", LIT(disabled));
gb_exit(1);
}
+
+ // NOTE(laytan): some weird errors on LLVM 14 that LLVM 17 fixes.
+ if (LLVM_VERSION_MAJOR < 17) {
+ gb_printf_err("Invalid LLVM version %s, RISC-V targets require at least LLVM 17\n", LLVM_VERSION_STRING);
+ gb_exit(1);
+ }
}
if (build_context.show_debug_messages) {