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* core/simd/x86: Add the AES-NI intrinsicsYawning Angel2024-06-011-0/+49
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* Correct `core:intrinsics` to `base:intrinsics`gingerBill2024-05-136-6/+6
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* compiler: improve target features supportLaytan Laats2024-05-022-4/+4
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* Replace `core:*` to `base:*` where appropriategingerBill2024-01-281-2/+2
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* core/simd/x86: Use the `none` calling convention for intrinsicsYawning Angel2024-01-0711-11/+11
| | | | | | | | The LLVM intrinsics that live under `llvm.x86` are not actual functions, so trying to invoke them as such using the platform's native C calling convention causes incorrect types to be emitted in the IR. Thanks to laytanl for assistance in testing.
* core/simd/x86: Correct a target feature nameYawning Angel2024-01-071-1/+1
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* Fix the other bit_* intrinsic callsjakubtomsu2023-10-222-7/+7
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* change and_not to bit_and_notjakubtomsu2023-10-221-1/+1
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* Rename simd bitwise operations from `intrinsics.simd_and` to ↵gingerBill2023-09-281-4/+4
| | | | `intrinsics.simd_bit_and` etc
* [sys/info] Initial version.Jeroen van Rijn2022-09-011-94/+0
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* Remove `simd_rem`; Disallow `simd_div` for integersgingerBill2022-06-021-2/+1
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* Add enable_target_feature to ABMgingerBill2022-05-301-4/+4
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* Add SSE4.2gingerBill2022-05-301-0/+149
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* Add `@(require_results)` to all appropriate proceduresgingerBill2022-05-3010-386/+398
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* Add SSE4.1gingerBill2022-05-301-0/+352
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* `@(require_target_feature=<string>)` `@(enable_target_feature=<string>)`gingerBill2022-05-307-0/+364
| | | | | require_target_feature - required by the target micro-architecture enable_target_feature - will be enabled for the specified procedure only
* Rename to `lanes_rotate_left`, `lanes_rotate_right`, `lanes_reverse`gingerBill2022-05-291-3/+3
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* Use single line attributesgingerBill2022-05-299-18/+9
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* Add sha.odingingerBill2022-05-291-0/+43
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* Add cmpxchg16bgingerBill2022-05-291-0/+8
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* Add pclmulqdq.odingingerBill2022-05-291-0/+13
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* Add rdtsc.odingingerBill2022-05-291-0/+19
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* Add fxsr.odingingerBill2022-05-292-2/+33
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* Add adx.odingingerBill2022-05-291-0/+53
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* Add abm.odingingerBill2022-05-291-0/+20
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* Add amd64 specific instructionsgingerBill2022-05-292-0/+64
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* Add `cpu_features` for `core:simd/x86`gingerBill2022-05-281-0/+94
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* Add `intrinsics.x86_cpuid` and `intrinsics.x86_xgetbv`gingerBill2022-05-281-1/+2
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* Add ssse3 supportgingerBill2022-05-271-0/+124
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* Add SSE3 supportgingerBill2022-05-271-0/+58
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* Rename to `non_temporaral_*`gingerBill2022-05-272-4/+4
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* Complete SSE2gingerBill2022-05-271-23/+309
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* Add pack and unpackgingerBill2022-05-271-0/+95
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* Add load and stores and setsgingerBill2022-05-271-0/+75
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* Add more sse2 intrinsicsgingerBill2022-05-271-22/+87
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* Add shiftsgingerBill2022-05-273-97/+233
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* Begin work on sse2.odingingerBill2022-05-271-0/+274
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* Add `_mm_stream_ps`gingerBill2022-05-271-0/+4
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* Change package namegingerBill2022-05-272-4/+4
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* Add `core:simd/x86` SSEgingerBill2022-05-272-0/+544
| | | | Proof of Concept to show intrinsics specific to a certain target platform
* Add loads of aliases of vector typesgingerBill2022-05-271-18/+53
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* Add prefix of `lanes_`gingerBill2022-05-261-2/+2
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* Support reverse_bits for #simdgingerBill2022-05-261-1/+2
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* Merge `intrinsics.simd_sqrt` with `intrinsics.sqrt`gingerBill2022-05-261-1/+1
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* Add `intrinsics.fused_mul_add`gingerBill2022-05-261-0/+3
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* Support `count_ones` etc with #simdgingerBill2022-05-261-5/+10
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* Rename `simd_eq` etc to `simd_lanes_eq`gingerBill2022-05-261-6/+6
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* Add arithmetic operator support for simd vectors; Add `intrinsics.simd_and_not`gingerBill2022-05-261-3/+13
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* Remove need for `simd.splat`gingerBill2022-05-261-7/+2
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* Keep -vet happygingerBill2022-05-261-1/+1
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