From dd5b7852ce569027e87d77f46601210aa4180947 Mon Sep 17 00:00:00 2001 From: Barinzaya Date: Mon, 5 May 2025 15:13:10 -0400 Subject: Added alternate reduce-add/reduce-mul intrinsics. The new reduce_add/reduce_mul procs perform the corresponding arithmetic reduction in different orders than sequential order. These alternative orders can often offer better SIMD hardware utilization. Two different orders are added: pair-wise (operating on pairs of adjacent elements) or bisection-wise (operating element-wise on the first and last N/2 elements of the vector). --- src/check_builtin.cpp | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/check_builtin.cpp') diff --git a/src/check_builtin.cpp b/src/check_builtin.cpp index a315d1880..84e30d5b4 100644 --- a/src/check_builtin.cpp +++ b/src/check_builtin.cpp @@ -853,8 +853,12 @@ gb_internal bool check_builtin_simd_operation(CheckerContext *c, Operand *operan } break; + case BuiltinProc_simd_reduce_add_bisect: + case BuiltinProc_simd_reduce_mul_bisect: case BuiltinProc_simd_reduce_add_ordered: case BuiltinProc_simd_reduce_mul_ordered: + case BuiltinProc_simd_reduce_add_pairs: + case BuiltinProc_simd_reduce_mul_pairs: case BuiltinProc_simd_reduce_min: case BuiltinProc_simd_reduce_max: { -- cgit v1.2.3