From 28c643d23f989937c8d530b49a2369e8cd9d39e2 Mon Sep 17 00:00:00 2001 From: Laytan Date: Sun, 1 Sep 2024 15:51:39 +0200 Subject: riscv compiler support --- src/threading.cpp | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/threading.cpp') diff --git a/src/threading.cpp b/src/threading.cpp index e30a20a06..af8fd803c 100644 --- a/src/threading.cpp +++ b/src/threading.cpp @@ -529,6 +529,9 @@ gb_internal gb_inline void yield_thread(void) { _mm_pause(); #elif defined(GB_CPU_ARM) __asm__ volatile ("yield" : : : "memory"); +#elif defined(GB_CPU_RISCV) + // I guess? + __asm__ volatile ("nop" : : : "memory"); #else #error Unknown architecture #endif -- cgit v1.2.3