sys/info: more CPU feature detection for RISC-V

4 files changed, 117 insertions, 0 deletions

diff --git a/core/sys/linux/bits.odin b/core/sys/linux/bits.odin
index f78891bc8..8a4a6dd7a 100644
--- a/core/sys/linux/bits.odin
+++ b/core/sys/linux/bits.odin
@@ -1839,3 +1839,87 @@ Execveat_Flags_Bits :: enum {
 	AT_SYMLINK_NOFOLLOW = 8,
 	AT_EMPTY_PATH       = 12,
 }
+
+RISCV_HWProbe_Key :: enum i64 {
+	UNSUPPORTED            = -1,
+	MVENDORID              = 0,
+	MARCHID                = 1,
+	MIMPID                 = 2,
+	BASE_BEHAVIOR          = 3,
+	IMA_EXT_0              = 4,
+ 	// Deprecated, try `.MISALIGNED_SCALAR_PERF` first, if that is `.UNSUPPORTED`, use this.
+	CPUPERF_0              = 5,
+	ZICBOZ_BLOCK_SIZE      = 6,
+	HIGHEST_VIRT_ADDRESS   = 7,
+	TIME_CSR_FREQ          = 8,
+	MISALIGNED_SCALAR_PERF = 9,
+}
+
+RISCV_HWProbe_Flags_Bits :: enum {
+	WHICH_CPUS,
+}
+
+RISCV_HWProbe_Base_Behavior_Bits :: enum {
+	IMA,
+}
+
+RISCV_HWProbe_IMA_Ext_0_Bits :: enum {
+	FD,
+	C,
+	V,
+	EXT_ZBA,
+	EXT_ZBB,
+	EXT_ZBS,
+	EXT_ZICBOZ,
+	EXT_ZBC,
+	EXT_ZBKB,
+	EXT_ZBKC,
+	EXT_ZBKX,
+	EXT_ZKND,
+	EXT_ZKNE,
+	EXT_ZKNH,
+	EXT_ZKSED,
+	EXT_ZKSH,
+	EXT_ZKT,
+	EXT_ZVBB,
+	EXT_ZVBC,
+	EXT_ZVKB,
+	EXT_ZVKG,
+	EXT_ZVKNED,
+	EXT_ZVKNHA,
+	EXT_ZVKNHB,
+	EXT_ZVKSED,
+	EXT_ZVKSH,
+	EXT_ZVKT,
+	EXT_ZFH,
+	EXT_ZFHMIN,
+	EXT_ZIHINTNTL,
+	EXT_ZVFH,
+	EXT_ZVFHMIN,
+	EXT_ZFA,
+	EXT_ZTSO,
+	EXT_ZACAS,
+	EXT_ZICOND,
+	EXT_ZIHINTPAUSE,
+	EXT_ZVE32X,
+	EXT_ZVE32F,
+	EXT_ZVE64X,
+	EXT_ZVE64F,
+	EXT_ZVE64D,
+	EXT_ZIMOP,
+	EXT_ZCA,
+	EXT_ZCB,
+	EXT_ZCD,
+	EXT_ZCF,
+	EXT_ZCMOP,
+	EXT_ZAWRS,
+}
+
+RISCV_HWProbe_Misaligned_Scalar_Perf :: enum {
+	UNKNOWN,
+	EMULATED,
+	SLOW,
+	FAST,
+	UNSUPPORTED,
+}
+
diff --git a/core/sys/linux/sys.odin b/core/sys/linux/sys.odin
index 6e4194be7..5ee07a93d 100644
--- a/core/sys/linux/sys.odin
+++ b/core/sys/linux/sys.odin
@@ -2993,3 +2993,18 @@ epoll_pwait2 :: proc(epfd: Fd, events: [^]EPoll_Event, count: i32, timeout: ^Tim
 // TODO(flysand): fchmodat2
 
 // TODO(flysand): map_shadow_stack
+
+when ODIN_ARCH == .riscv64 {
+	/*
+		Probe for RISC-V Hardware Support.
+		Available since Linux 6.4.
+
+		TODO: cpu_set_t
+
+		See: https://docs.kernel.org/arch/riscv/hwprobe.html
+	*/
+	riscv_hwprobe :: proc "contextless" (pairs: [^]RISCV_HWProbe, pair_count: uint, cpu_count: uint, cpus: rawptr /* cpu_set_t */, flags: RISCV_HWProbe_Flags) -> Errno {
+		ret := syscall(SYS_riscv_hwprobe, pairs, pair_count, cpu_count, cpus, transmute(u32)flags)
+		return Errno(-ret)
+	}
+}
diff --git a/core/sys/linux/syscall_riscv64.odin b/core/sys/linux/syscall_riscv64.odin
index ce374312e..d2fd0c2ff 100644
--- a/core/sys/linux/syscall_riscv64.odin
+++ b/core/sys/linux/syscall_riscv64.odin
@@ -248,6 +248,7 @@ SYS_rt_tgsigqueueinfo            :: uintptr(240)
 SYS_perf_event_open              :: uintptr(241)
 SYS_accept4                      :: uintptr(242)
 SYS_recvmmsg                     :: uintptr(243)
+SYS_riscv_hwprobe                :: uintptr(258)
 SYS_wait4                        :: uintptr(260)
 SYS_prlimit64                    :: uintptr(261)
 SYS_fanotify_init                :: uintptr(262)
diff --git a/core/sys/linux/types.odin b/core/sys/linux/types.odin
index 3f873f96c..0e5b8218b 100644
--- a/core/sys/linux/types.odin
+++ b/core/sys/linux/types.odin
@@ -1335,3 +1335,20 @@ EPoll_Event :: struct #packed {
 	Flags for execveat(2) syscall.
 */
 Execveat_Flags :: bit_set[Execveat_Flags_Bits; i32]
+
+RISCV_HWProbe_Flags         :: bit_set[RISCV_HWProbe_Flags_Bits; u32]
+RISCV_HWProbe_CPU_Perf_0    :: bit_set[RISCV_HWProbe_Misaligned_Scalar_Perf; u64]
+RISCV_HWProbe_Base_Behavior :: bit_set[RISCV_HWProbe_Base_Behavior_Bits; u64]
+RISCV_HWProbe_IMA_Ext_0     :: bit_set[RISCV_HWProbe_IMA_Ext_0_Bits; u64]
+
+RISCV_HWProbe :: struct {
+ 	// set to `.UNSUPPORTED` by the kernel if that is the case.
+	key:   RISCV_HWProbe_Key,
+	value: struct #raw_union {
+		base_behavior:          RISCV_HWProbe_Base_Behavior,
+		ima_ext_0:              RISCV_HWProbe_IMA_Ext_0,
+		cpu_perf_0:             RISCV_HWProbe_CPU_Perf_0,
+		misaligned_scalar_perf: RISCV_HWProbe_Misaligned_Scalar_Perf,
+		raw:                    u64,
+	},
+}