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| author | Barinzaya <barinzaya@gmail.com> | 2025-05-05 15:13:10 -0400 |
|---|---|---|
| committer | Barinzaya <barinzaya@gmail.com> | 2025-05-05 16:38:45 -0400 |
| commit | dd5b7852ce569027e87d77f46601210aa4180947 (patch) | |
| tree | c9ba26ed3bc8666c8dbebec1faeba3e7839b5c08 /src/llvm_backend.cpp | |
| parent | 981437065968214430a2f958705affa9a15a09ae (diff) | |
Added alternate reduce-add/reduce-mul intrinsics.
The new reduce_add/reduce_mul procs perform the corresponding arithmetic
reduction in different orders than sequential order. These alternative
orders can often offer better SIMD hardware utilization.
Two different orders are added: pair-wise (operating on pairs of
adjacent elements) or bisection-wise (operating element-wise on the
first and last N/2 elements of the vector).
Diffstat (limited to 'src/llvm_backend.cpp')
0 files changed, 0 insertions, 0 deletions