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| author | gingerBill <gingerBill@users.noreply.github.com> | 2024-09-02 00:20:04 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-09-02 00:20:04 +0100 |
| commit | 16c5c69a4079652e930d897823446b7e7a65bd2f (patch) | |
| tree | 2543c3c65ca653bcc0ed13da59775d4b314d57e7 /src/threading.cpp | |
| parent | 39b49cb6fbf5f717bb0b01c6449d37f99ffd9b48 (diff) | |
| parent | 28c643d23f989937c8d530b49a2369e8cd9d39e2 (diff) | |
Merge pull request #4175 from laytan/riscv-compilerdev-2024-09
Support RISC-V for the compiler itself
Diffstat (limited to 'src/threading.cpp')
| -rw-r--r-- | src/threading.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/threading.cpp b/src/threading.cpp index e30a20a06..af8fd803c 100644 --- a/src/threading.cpp +++ b/src/threading.cpp @@ -529,6 +529,9 @@ gb_internal gb_inline void yield_thread(void) { _mm_pause(); #elif defined(GB_CPU_ARM) __asm__ volatile ("yield" : : : "memory"); +#elif defined(GB_CPU_RISCV) + // I guess? + __asm__ volatile ("nop" : : : "memory"); #else #error Unknown architecture #endif |