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| author | Barinzaya <barinzaya@gmail.com> | 2025-05-03 11:42:24 -0400 |
|---|---|---|
| committer | Barinzaya <barinzaya@gmail.com> | 2025-05-03 11:55:52 -0400 |
| commit | 7e34d707bb710eae6b764fc1e792c17eb879f1f8 (patch) | |
| tree | baf7101ddd14997d206e897fccc787b7640ecc3a /src | |
| parent | 9681d88cd3d801f56456bdbe91fe437ebcda96cb (diff) | |
`core:simd` helpers: indices and reduce_add/mul
The indices proc simply creates a vector where each lane contains its
own lane index. This can be useful for use in generating masks for loads
and stores at the beginning/end of slices, among other things.
The new reduce_add/reduce_mul procs perform the corresponding arithmetic
reduction, in different orders than just "in sequential order". These
alternative orders can often be faster to calculate, as they can offer
better SIMD hardware utilization.
Two different orders are added for these: pair-wise (operating on
adjacent pairs of elements) or split-wise (operating element-wise on the
two halves of the vector).
This doesn't actually cover the *fastest* way for arbitrarily-sized
vectors. That would be an ordered reduction across the native vector
width, then reducing the resulting vector to a scalar in an appropriate
parallel fashion. I'd created an implementation of that, but it required
multiple procs and a fair bit more trickery than I was comfortable with
submitting to `core`, so it's not included yet. Maybe in the future.
Diffstat (limited to 'src')
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