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authorLaytan <laytanlaats@hotmail.com>2025-07-31 20:26:22 +0200
committerLaytan <laytanlaats@hotmail.com>2025-07-31 20:26:22 +0200
commitc3bae964d0223121985a52d3c860f879f842f0d3 (patch)
treea29872f6c759b6d84ee81669720ee4f2f9268552 /src
parent939fed592dfcd27e7eb14e4222a90a5b7852c0d7 (diff)
amd64 abi fixes regarding vectors
- Fixes the code so SSEUp is grouped/skipped over properly (Fixes #5429) - Fixes f16 vectors using garbage widths, because it would call LLVMGetIntTypeWidth and an f16 is not an int so doesn't have that function
Diffstat (limited to 'src')
-rw-r--r--src/llvm_abi.cpp25
1 files changed, 16 insertions, 9 deletions
diff --git a/src/llvm_abi.cpp b/src/llvm_abi.cpp
index e1cbe7558..c4c5b5a63 100644
--- a/src/llvm_abi.cpp
+++ b/src/llvm_abi.cpp
@@ -850,14 +850,18 @@ namespace lbAbiAmd64SysV {
} else if (oldv == RegClass_SSEUp) {
oldv = RegClass_SSEDv;
} else if (is_sse(oldv)) {
- i++;
- while (i != e && oldv == RegClass_SSEUp) {
- i++;
+ for (i++; i < e; i++) {
+ RegClass v = (*cls)[cast(isize)i];
+ if (v != RegClass_SSEUp) {
+ break;
+ }
}
} else if (oldv == RegClass_X87) {
- i++;
- while (i != e && oldv == RegClass_X87Up) {
- i++;
+ for (i++; i < e; i++) {
+ RegClass v = (*cls)[cast(isize)i];
+ if (v != RegClass_X87Up) {
+ break;
+ }
}
} else {
i++;
@@ -1046,10 +1050,9 @@ namespace lbAbiAmd64SysV {
i64 elem_sz = lb_sizeof(elem);
LLVMTypeKind elem_kind = LLVMGetTypeKind(elem);
RegClass reg = RegClass_NoClass;
- unsigned elem_width = LLVMGetIntTypeWidth(elem);
switch (elem_kind) {
- case LLVMIntegerTypeKind:
- case LLVMHalfTypeKind:
+ case LLVMIntegerTypeKind: {
+ unsigned elem_width = LLVMGetIntTypeWidth(elem);
switch (elem_width) {
case 8: reg = RegClass_SSEInt8; break;
case 16: reg = RegClass_SSEInt16; break;
@@ -1065,6 +1068,10 @@ namespace lbAbiAmd64SysV {
GB_PANIC("Unhandled integer width for vector type %u", elem_width);
}
break;
+ };
+ case LLVMHalfTypeKind:
+ reg = RegClass_SSEInt16;
+ break;
case LLVMFloatTypeKind:
reg = RegClass_SSEFv;
break;